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Integrated Circuit Systems, Inc.
ICS83948I-147
LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
FEATURES
* Twelve LVCMOS/LVTTL outputs * Selectable LVCMOS/LVTTL clock or differential CLK, nCLK inputs * CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL * LVCMOS_CLK accepts the following input levels: LVCMOS or LVTTL * Output frequency: 350MHz (maximum) * Output skew (at 3.3V 5%): 100ps (maximum) * Part-to-part skew (at 3.3V 5%): 1ns (maximum) * Full 3.3V or full 2.5V operating supply * -40C to 85C ambient operating temperature * Available in both standard and lead-free RoHS-compliant packages
GENERAL DESCRIPTION
The ICS83948I-147 is a low skew, 1-to-12 Differential-to-LVCMOS/LVTTL Fanout Buffer and HiPerClockSTM a member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS83948I-147 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The LVCMOS_CLK can accept LVCMOS or LVTTL input levels. The low impedance LVCMOS/LVTTL outputs are designed to drive 50 series or parallel terminated transmission lines. The effective fanout can be increased from 12 to 24 by utilizing the ability of the outputs to drive two series terminated lines.
IC S
The ICS83948I-147 is characterized at full 3.3V or full 2.5V operating supply modes. Guaranteed output and part-to-part skew characteristics make the ICS83948I-147 ideal for those clock distribution applications demanding well defined performance and repeatability.
BLOCK DIAGRAM
CLK_EN D Q LE LVCMOS_CLK CLK nCLK 1 Q0 0 Q1 CLK_SEL Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 OE
PIN ASSIGNMENT
GND GND VDDO VDDO Q0 Q1 Q2 Q3
32 31 30 29 28 27 26 25 CLK_SEL LVCMOS_CLK CLK nCLK CLK_EN OE VDD GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Q11 VDDO Q10 GND Q9 VDDO Q8 GND
24 23 22
GND Q4 VDDO Q5 GND Q6 VDDO Q7
ICS83948I-147
21 20 19 18 17
32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View
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REV. B NOVEMBER 21, 2005
Integrated Circuit Systems, Inc.
ICS83948I-147
LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Type Input Input Input Input Input Input Power Power Output Power Pullup Pullup Pullup Pullup Pullup Description Clock select input. Selects LVCMOS_CLK input when HIGH. Selects CLK, nCLK inputs when LOW. LVCMOS/LVTTL interface levels Clock input. LVCMOS/LVTTL interface levels. Non-inver ting differential clock input. Clock enable. LVCMOS/ LVTTL interface levels. Output enable. LVCMOS/LVTTL interface levels. Power supply pin. Power supply ground. Clock outputs. LVCMOS/LVTTL interface levels. Output supply pins.
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3 4 5 6 7 8, 12, 16, 20, 24, 28, 32 9, 11, 13, 15, 17, 19, 21, 23 25, 27, 29, 31 10, 14, 18, 22, 26, 30 Name CLK_SEL LVCMOS_CLK CLK nCLK CLK_EN OE VDD GND Q11, Q10, Q9, Q8, Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0 VDDO
Pulldown Inver ting differential clock input.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN CPD RPULLUP RPULLDOWN ROUT Parameter Input Capacitance Power Dissipation Capacitance (per output) Input Pullup Resistor Input Pulldown Resistor Output Impedance 5 Test Conditions Minimum Typical 4 12 51 51 7 12 Maximum Units pF pF k k
TABLE 3A. CLOCK SELECT FUNCTION TABLE
Control Input 0 1 Clock CLK, nCLK inputs selected LVCMOS_CLK input selected
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs CLK_SEL 0 0 0 0 0 0 1 1 LVCMOS_CLK -- -- -- -- -- -- 0 1 CLK 0 1 0 1 Biased; NOTE 1 Biased; NOTE 1 -- -- nCLK 1 0 Biased; NOTE 1 Biased; NOTE 1 0 1 -- -- Outputs Q0:Q11 LOW HIGH LOW HIGH HIGH LOW LOW HIGH Input to Output Mode Differential to Single Ended Differential to Single Ended Single Ended to Single Ended Single Ended to Single Ended Single Ended to Single Ended Single Ended to Single Ended Single Ended to Single Ended Single Ended to Single Ended Polarity Non Inver ting Non Inver ting Non Inver ting Non Inver ting Inver ting Inver ting Non Inver ting Non Inver ting
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
83948AYI-147
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REV. B NOVEMBER 21, 2005
Integrated Circuit Systems, Inc.
ICS83948I-147
LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
4.6V -0.5V to VDD + 0.5 V -0.5V to VDDO + 0.5V 47.9C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = -40 TO 85
Symbol VDD VDDO IDD Parameter Power Supply Voltage Output Supply Voltage Power Supply Current Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 Maximum 3.465 3.465 55 Units V V mA
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 2.5V5%, TA = -40 TO 85
Symbol VDD VDDO IDD Parameter Power Supply Voltage Output Supply Voltage Power Supply Current Test Conditions Minimum 2.375 2.375 Typical 2.5 2.5 Maximum 2.625 2.625 52 Units V V mA
TABLE 4C. DC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = -40 TO 85
Symbol Parameter VIH VIL IIN VOH VOL VPP Input High Voltage Input Low Voltage Input Current Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 LVCMOS LVCMOS VIN = VDD or VIN = GND IOH = -24mA IOL = 24mA IOL = 12mA 2.4 0.55 0.30 1.3 VDD - 0.85 Test Conditions Minimum 2 -0.3 Typical Maximum VDD + 0.3 0.8 300 Units V V A V V V V V
Peak-to-Peak Input Voltage CLK, nCLK 0.15 Input Common Mode Voltage; VCMR CLK, nCLK GND + 0.5 NOTE 2, 3 NOTE 1: Outputs capable of driving 50 transmission lines terminated with 50 to VDDO/2. See Parameter Measurement section, "3.3V Output Load AC Test Circuit". NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V. NOTE 3: Common mode voltage is defined as VIH.
83948AYI-147
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REV. B NOVEMBER 21, 2005
Integrated Circuit Systems, Inc.
ICS83948I-147
LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Test Conditions LVCMOS LVCMOS VIN = VDD or VIN = GND IOH = -15mA IOL = 15mA 1.8 0.6 1.3 VDD - 0.85 Minimum 1.7 -0.3 Typical Maximum VDD + 0.3 0.7 300 Units V V A V V V V
TABLE 4D. DC CHARACTERISTICS, VDD = VDDO = 2.5V5%, TA = -40 TO 85
Symbol VIH VIL IIN VOH VOL VPP Parameter Input High Voltage Input Low Voltage Input Current Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1
Peak-to-Peak Input Voltage CLK, nCLK 0.15 Input Common Mode Voltage; VCMR CLK, nCLK GND + 0.5 NOTE 2, 3 NOTE 1: Outputs capable of driving 50 transmission lines terminated with 50 to VDDO/2. See Parameter Measurement section, "2.5V Output Load AC Test Circuit". NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V. NOTE 3: Common mode voltage is defined as VIH.
TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = -40 TO 85
Symbol Parameter fMAX Output Frequency tPD Propagation Delay; CLK, nCLK; NOTE 1 LVCMOS_CLK; NOTE 2 Test Conditions Minimum Typical Maximum 350 4 4 100 1 0.2 45 50 1.0 55 5 Units MHz ns ns ps ns ns % ns ns ns ns ns ns
350MHz 350MHz Measured on rising edge @VDDO/2 Measured on rising edge @VDDO/2 0.8V to 2V 150MHz, Ref = CLK, nCLK
2 2
t sk(o) t sk(pp) tR / tF odc tPZL, tPZH tPLZ, tPHZ
Output Skew; NOTE 3, 7 Par t-to-Par t Skew; NOTE 4, 7 Output Rise/Fall Time Output Duty Cycle Output Enable Time; NOTE 5
Output Disable Time; NOTE 5 5 CLK_EN to 1 Clock Enable CLK, nCLK tS Setup Time; CLK_EN to NOTE 6 0 LVCMOS_CLK CLK, nCLK to 0 Clock Enable CLK_EN tH Hold Time; LVCMOS_CLK NOTE 6 1 to CLK_EN NOTE 1: Measured from the differential input crossing point to VDDO/2 of the output. NOTE 2: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. NOTE 6: Setup and Hold times are relative to the rising edge of the input clock. NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.
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REV. B NOVEMBER 21, 2005
Integrated Circuit Systems, Inc.
ICS83948I-147
LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Test Conditions Minimum Typical Maximum 350 4.2 4.4 160 2 0.1 40 1.0 60 5 Units MHz ns ns ps ns ns % ns ns ns ns ns ns
TABLE 5B. AC CHARACTERISTICS, VDD = VDDO = 2.5V5%, TA = -40 TO 85
Symbol Parameter fMAX Output Frequency tPD Propagation Delay; CLK, nCLK; NOTE 1 LVCMOS_CLK; NOTE 2
f 350MHz f 350MHz Measured on rising edge @VDDO/2 Measured on rising edge @VDDO/2 0.6V to 1.8V 150MHz, Ref = CLK, nCLK
1.5 1.7
tsk(o) tsk(pp) tR / tF odc tPZL, tPZH tPLZ, tPHZ
Output Skew; NOTE 3, 7 Par t-to-Par t Skew; NOTE 4, 7 Output Rise/Fall Time Output Duty Cycle Output Enable Time; NOTE 5
Output Disable Time; NOTE 5 5 CLK_EN to 1 Clock Enable CLK, nCLK tS Setup Time; CLK_EN to NOTE 6 0 LVCMOS_CLK CLK, nCLK to 0 Clock Enable CLK_EN tH Hold Time; LVCMOS_CLK NOTE 6 1 to CLK_EN NOTE 1: Measured from the differential input crossing point to VDDO/2 of the output. NOTE 2: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. NOTE 6: Setup and Hold times are relative to the rising edge of the input clock. NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.
83948AYI-147
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REV. B NOVEMBER 21, 2005
Integrated Circuit Systems, Inc.
ICS83948I-147
LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
1.65V 5% 1.25V5%
VDD, VDDO
SCOPE
Qx
VDD, VDDO
SCOPE
Qx
LVCMOS
GND
LVCMOS
GND
-1.65V 5%
-1.25V5%
3.3V OUTPUT LOAD AC TEST CIRCUIT
VDD
2.5V OUTPUT LOAD AC TEST CIRCUIT
V
nCLK Qx
DDO
2
V
CLK
PP
Cross Points
V
CMR
V
Qy
DDO
2 tsk(o)
GND
DIFFERENTIAL INPUT LEVEL
PART 1 Qx
OUTPUT SKEW
V
DDO
V
DDO
Q0:Q11
2
2
t PW
t
PERIOD
PART 2 Qy
V
DDO
2 tsk(pp)
odc =
t PW t PERIOD
x 100%
PART-TO-PART SKEW
2V 0.8V tR
VDD = VDDO = 3.3V
odc & tPERIOD
2V
LVCMOS_CLK
VDD 2
Clock Outputs
0.8V tF
nCLK CLK
1.8V 0.6V tR
VDD = VDDO = 2.5V
1.8V 0.6V tF
Q0:Q11
VDDO 2 t
PD
Clock Outputs
OUTPUT RISE/FALL TIME
83948AYI-147
PROPAGATION DELAY
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REV. B NOVEMBER 21, 2005
Integrated Circuit Systems, Inc.
ICS83948I-147
LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u
R2 1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS:
CLK INPUT: For applications not requiring the use of a clock input, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the CLK input to ground. CLK/nCLK INPUT: For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from CLK to ground. LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used.
83948AYI-147
LVCMOS OUTPUT: All unused LVCMOS output can be left floating. We recommend that there is no trace attached.
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REV. B NOVEMBER 21, 2005
Integrated Circuit Systems, Inc.
ICS83948I-147
LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER RELIABILITY INFORMATION
TABLE 6. JAVS. AIR FLOW TABLE FOR 32 LEAD LQFP
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS83948I-147 is: 1040 Pin compatible with the MPC9448
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REV. B NOVEMBER 21, 2005
Integrated Circuit Systems, Inc.
ICS83948I-147
LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L ccc 0.45 0 --0.05 1.35 0.30 0.09 MINIMUM NOMINAL 32 --1.40 0.37 -9.00 BASIC 7.00 BASIC 5.60 Ref. 9.00 BASIC 7.00 BASIC 5.60 Ref. 0.80 BASIC 0.60 --0.75 7 0.10 1.60 0.15 1.45 0.45 0.20 MAXIMUM
REFERENCE DOCUMENT: JEDEC PUBLICATION 95, MS-026
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REV. B NOVEMBER 21, 2005
Integrated Circuit Systems, Inc.
ICS83948I-147
LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Marking Package 32 Lead LQFP 32 Lead LQFP 32 Lead "Lead-Free" LQFP 32 Lead "Lead-Free" LQFP Shipping Packaging tray 1000 tape & reel tray 1000 tape & reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C
TABLE 8. ORDERING INFORMATION
Part/Order Number ICS83948AYI-147 ICS83948AYI-147T ICS83948AYI-147LF ICS83948AYI-147LFT ICS83948AI147 ICS83948AI147 ICS948AI147L ICS948AI147L
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 83948AYI-147
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REV. B NOVEMBER 21, 2005
Integrated Circuit Systems, Inc.
ICS83948I-147
LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
REVISION HISTORY SHEET Description of Change Features Sectiton - added Lead-Free bullet. Pin Chararcteristics Table - changed CIN from 4pF max. to 4pF typical; and added 5 min. and 12 max to ROUT. Updated Single Ended Signal Driving Differential Input diagram Added Recommendations for Unused Input and Output Pins. Ordering Information Table - added lead-free par t number, marking, and note. Date
Rev
Table T2
Page 1 2 7
B T8
11/21/05
10
83948AYI-147
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